Description

RTL Design & Verification Engineer

Certified RTL Design & Verification Engineer

This course is an exclusively designed course by industry experts to train you on the advanced Design and Verification technologies and methodologies i.e. RTL Design, FPGA design methodologies, FPGA Architecture, Advanced Verilog for Verification, Verification Methodologies, System Verilog, UVM, Assertion Based Verification – SVA, Verification Planning and Management, Code and Functional Coverage. One can easily enter into the VLSI industry with the skill sets that are gained through this training course.

Curriculum

MODULE 1:
Introduction to VLSI
  • VLSI Design Flow
  • ASIC Vs FPGA
  • RTL Design Methodologies
  • Introduction to Verification Methodologies
  • VLSI Design Flow Steps – Demo
MODULE 2:
Advanced Digital Design
  • Introduction to Digital Electronics
  • Arithmetic Circuits
  • Data processing Circuits
  • Universal Logic Elements
  • Combinational Circuits – Design and Analysis
  • Latches and Flip flops
  • Shift Registers and Counters
  • Sequential Circuits – Design and Analysis
  • Memories and PLD
  • Finite State Machine
  • Microcontroller Design
MODULE 3:
CMOS Fundamentals
  • Non Ideal characteristics
  • BJT vs FET
  • CMOS Characteristics
  • CMOS circuit design
  • Transistor sizing
  • Layout and Stick Diagrams
  • CMOS Processing Steps
  • Fabrication
  • CMOS Technology – Current Trends
MODULE 4: Verilog HDL – RTL Coding and Synthesis [1] Introduction to Verilog HDL
  • Applications of Verilog HDL
  • Verilog HDL language concept
  • Verilog language basics and constructs
  • Abstraction levels
[2] Data Types
  • Type Concept
  • Nets and registers
  • Non hardware equivalent variables
  • Arrays
[3] Verilog Operators
  • Logical operators
  • Bitwise and Reduction operators
  • Concatenation and conditional
  • Relational and arithmetic
  • Shift and Equality operators
  • Operators precedence
[4] Assignments
  • Type of assignments
  • Continuous assignments
  • Timing references
  • Procedures
  • Blocking and Non-Blocking assignments
  • Execution branching
  • Tasks and Functions
[5] Finite State Machine
  • Basic FSM structure
  • Moore Vs Mealy
  • Common FSM coding styles
  • Registered outputs
[6] Advanced Verilog for Verification
  • System Tasks
  • Internal variable monitoring
  • Compiler directives
  • File input and output
[7] Synthesis Coding Style
  • Registers in Verilog
  • Unwanted latches
  • Operator synthesis
  • RTL Coding style
MODULE 5:
Code Coverage
  • Statement coverage
  • Branch Coverage
  • Expression Coverage
  • Path Coverage
  • Toggle Coverage
  • FSM – State, Arc and Sequence coverage
MODULE 6:
FPGA Architecture
[1] PLD
  • General Structure and Classification
  • CPLD Vs FPGA
[2] Xilinx CPLD – Xc9500
  • Block Diagram of CPLD
  • Detailed study of each block
  • Endurance limits
  • Timing Model
[3] Xilinx FPGA
  • FPGA Architecture
  • CLBs and Input/output Blocks
  • Luts,SLICE DFFs
  • Dedicated MUXes
  • Programmable Interconnects
  • Architectural Resources
  • Power Distribution and Configuration
[4] FPGA Architecture of Different Xilinx Families
[5] Netlist and Timing simulation
MODULE 7:
Verilog Mini Project RTL Coding and Synthesis
  • Project Specification Analysis
  • Understanding the architecture
  • Module level implementation and verification
  • Building the top-level module
  • Implementing the design into the FPGA board
MODULE 8:
SystemVerilog HVL
[1] Introduction to SystemVerilog
  • New Data types
  • Tasks and Functions
  • Interfaces
  • Clocking blocks
[2] Object Oriented Programming and Randomization
  • OOP Basics
  • Classes – Objects and handles
  • Polymorphism and Inheritance
  • Randomization
  • Constraints
[3] Threads and Virtual Interfaces
  • Fork Join
  • Fork Join_any
  • Fork Join_none
  • Event controls
  • Mailboxes and semaphores
  • Virtual Interfaces
  • Transactors
  • Building verification environment
  • Test cases
[4] Callbacks
  • Facade Class
  • Building Reusable Transactors
  • Inserting Callbacks
[5] Direct Programming Interface
[6] Functional Coverage
  • Coverage models
  • Coverpoints and bins
  • Cross coverage
MODULE 9:
Verification Planning and Management
  • Verification Plan
  • TB Architecture
  • Coverage Model
  • Tracking the simulation process
  • Building regression test suite
  • Test suite optimization
MODULE 10:
Advanced SystemVerilog
  • Environment Configuration
  • Reference Models and Predictor Logics
  • Using Legacy BFMs
  • Scenario Generation
  • Test cases – Random
  • Directed and corner case
  • Coding styles for VIP
MODULE 11:
Assertion Based Verification – SVA
  • Introduction to ABV
  • Immediate Assertions
  • Simple Assertions
  • Sequences
  • Sequence Composition
  • Advanced SVA Features
  • Assertion Coverage
MODULE 12:
Verification Mini Project
  • Verification and RTL sign-off
  • Project specification analysis
  • Defining verification plan
  • Creating Test bench architecture
  • Defining Transaction
  • Implementing the transactors – Generator, Driver, Receiver and Scoreboard
  • Implementing the coverage model
  • Building the top level verification environment
  • Defining weighted random, corner case and directed test cases
  • Building the regression test suite
  • Generating the functional and code coverage reports
MODULE 13:
UVM – Universal Verification Methodology
  • Introduction to UVM Methodology
  • Overview of Project
  • UVM TB Architecture
  • Stimulus Modeling
  • Creating UVCs and Environment
  • UVM Simulation Phases
  • Testcase Classes
  • TLM Overview
  • Configuring TB Environment
  • UVM Sequences
  • UVM Sequencers
  • Connecting DUT- Virtual Interface
  • Virtual Sequences and Sequencers
  • Creating TB Infrastructure
  • Connecting multiple UVCs
  • Building a Scoreboard
  • Introduction to Register Modeling
  • Building reusable environments
MODULE 14:
Interfaces and Protocols
  • UART, I2C, SPI IP Design & Verification
  • Guest Lectures by Industry Experts
MODULE 15:
Industry Standard Project
  • Design specification analysis
  • Creating the design architecture
  • Partitioning the design
  • RTL coding in Verilog
  • RTL functional verification
  • RTL Synthesis
  • Place & Route the netlist
  • Timing Simulation
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  • Duration 04 hours
  • Lessons0
  • Skill levelAll Levels
  • CategoryElectrical Courses

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